Y. Masuda, Y. Honda, and T. Ishihara, “Dynamic Verification Framework of Approximate Computing Circuits using Quality-aware Coverage-based Grey-box Fuzzing,” IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, vol.E106-A, No.3, pp.514-522, Mar. 2023.
L. Hou, Y. Masuda, and T. Ishihara, “An Accuracy Reconfigurable Vector Accelerator based on Approximate Logarithmic Multipliers for Energy-Efficient Computing,” IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, vol.E106-A, No.3, pp.532-541, Mar. 2023.
Y. Masuda, J. Nagayama, T. Cheng, T. Ishihara, Y. Momiyama, and M. Hashimoto, “Low-Power Design Methodology of Voltage Over-Scalable Circuit with Critical Path Isolation and Bit-Width Scaling,” IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol.E105-A, No.3, pp.509-517, Mar. 2022.
T. Komori, Y. Masuda, J. Shiomi, and T. Ishihara, “Approximate Minimum Energy Point Tracking and Task Scheduling for Energy-Efficient Real-Time Computing,” IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol.E105-A, No.3, pp.497-508, Mar. 2022.
T. Y. Cheng, Y. Masuda, J. Nagayama, Y. Momiyama, J. Chen, and M. Hashimoto, “Activation-aware Slack Assignment Based Mode-wise Voltage Scaling for Energy Minimization,” IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol.E105-A, No.3, pp.518-529, Mar. 2022.
N. Hattori, J. Shiomi, Y. Masuda, T. Ishihara, A. Shinya, and M. Notomi, “Neural Network Calculations at the Speed of Light Using Optical Vector-Matrix Multiplication and Optoelectronic Activation,” IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol. E104-A, No.11, pp.1477-1487, Nov. 2021.
T. Y. Cheng, Y. Masuda, J. Chen, J. Yu, and M. Hashimoto, “Logarithm-Approximate Floating-Point Multiplier is Applicable to Power-Efficient Neural Network Training,’’ Integration, the VLSI Journal, vol. 74, pp. 19-31, Sep. 2020.
Y. Masuda and M. Hashimoto, “MTTF-aware Design Methodology of Adaptively Voltage Scaled Circuit with Timing Error Predictive Flip-Flop,” IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, vol. E102-A, no. 7, pp. 867-877, July 2019.
Y. Masuda, T. Onoye, and M. Hashimoto, “Activation-aware slack assignment for time-to-failure extension and power saving,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 26, no. 11, pp. 2217-2229, Nov. 2018.
Y. Masuda, T. Onoye, and M. Hashimoto, “Performance evaluation of software-based error detection mechanisms for supply noise induced timing errors,” IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, vol. E100-A, no. 7, pp. 1452-1463, July 2017.
International Conference Papers
Y. Honda, Y. Masuda, and T. Ishihara, “Feedback-tuned fuzzing for accelerating quality verification of
approximate computing design,” Proc. 29th International Symposium on On-Line Testing and Robust System Design (IOLTS), July 2023. (accepted, to appear)
J. Lu, Y. Masuda, and T. Ishihara, “An Efficient Fault Injection Algorithm for Identifying Unimportant FFs in Approximate Computing Circuits,” Proc. IEEE Design, Automation and Test in Europe Conference (DATE), Apr. 2023.
J. Lu, Y. Masuda, and T. Ishihara, “Importance Evaluation Methodology of FFs for Design Optimization of Approximate Computing Circuits,” Proc. 24th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI), pp. 20 – 25, Hirosaki, Aomori, Oct. 2022.
T. Komori, Y. Masuda, and T. Ishihara, “DVFS virtualization for energy minimization of mixed-criticality dual-OS platforms,” Proc. 28th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA), pp.128-137, Taipei, Taiwan, Aug. 2022.
N. Hattori, Y. Masuda, T. Ishihara, A. Shinya, and M. Notomi, “Power-Aware Pruning for Ultrafast, Energy-Efficient, and Accurate Optical Neural Network Design,” Proc. Design Automation Conference (DAC), pp. 1285 – 1290, San Francisco, CA, USA, July 2022.
T. Ichikawa, Y. Masuda, T. Ishihara, A. Shinya, and M. Notomi, “Optoelectronic Implementation of Compact and Power-Efficient Recurrent Neural Networks,” Proc. IEEE Computer Society Annual Symposium on VLSI (ISVLSI), pp. 390-393, July 2022.
L. Hou, Y. Masuda, and T. Ishihara, “An Accuracy Reconfigurable Vector Accelerator based on Approximate Logarithmic Multipliers,” Proc. Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 568 – 573, Jan. 2022.
K. Yoshisue, Y. Masuda, and T. Ishihara, “Dynamic Verification of Approximate Computing Circuits using Coverage-based Grey-box Fuzzing,” Proc. 2021 IEEE 27th International Symposium on On-Line Testing and Robust System Design (IOLTS), June 2021 (On-line).
T. Komori, Y. Masuda, J. Shiomi, and T. Ishihara, “Integration of Minimum Energy Point Tracking and Soft Real-Time Scheduling for Edge Computing,” Proc. IEEE International Symposium on Quality Electronic Design (ISQED), pp. 300 – 306, Apr. 2021 (On-line).
L. Hou, Y. Masuda, and T. Ishihara, “An Accuracy Reconfigurable Multiply-Accumulate Unit Based on Operand-Decomposed Mitchell’s Multiplier,” Proc. 23rd Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI), pp. 68-73, Mar. 2021 (On-line).
N. Hattori, Y. Masuda, T. Ishihara, J. Shiomi, A. Shinya, and M. Notomi, “Optical-electronic implementation of artificial neural network for ultrafast and accurate inference processing,” Proc. AI and Optical Data Sciences II. International Society for Optics and Photonics, Mar. 2021 (On-line).
Y. Masuda, J. Nagayama, T. Y. Cheng, T. Ishihara, Y. Momiyama, and M. Hashimoto, “Critical Path Isolation and Bit-Width Scaling Are Highly Compatible for Voltage Over-Scalable Design,” Proc. IEEE Design, Automation and Test in Europe Conference (DATE), pp. 1260-1265, Feb. 2021 (On-line).
T. Y. Cheng, Y. Masuda, J. Nagayama, Y. Momiyama, J. Chen, and M. Hashimoto, “Mode-wise Voltage-scalable Design with Activation-aware Slack Assignment for Energy Minimization,” Proc. Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 284-290, Jan. 2021 (On-line).
Y. Masuda, J. Nagayama, T. Y. Cheng, T. Ishihara, Y. Momiyama, and M. Hashimoto, “Variation-Tolerant Voltage Over-Scalable Design with Critical Path Isolation and Bit-Width Scaling,” International Workshop on Logic & Synthesis (IWLS), pp.136-142, July 2020 (On-line).
K. Kiyawat, Y. Masuda, J. Shiomi, and T. Ishihara, “Real-time Minimum Energy Point Tracking Using a Predetermined Optimal Voltage Setting Strategy,” Proc. IEEE Computer Society Annual Symposium on VLSI (ISVLSI), pp.415-421, July 2020 (On-line).
T. Ishihara, J. Shiomi, N. Hattori, Y. Masuda, A. Shinya, and M. Notomi, “An Optical Neural Network Architecture based on Highly Parallelized WDM-Multiplier-Accumulator,” Proc. IEEE/ACM Workshop on Photonics-Optics Technology Oriented Networking, Information and Computing Systems (PHOTONICS), Denver, CO, USA, pp. 15-21, Nov. 2019.
Y. Masuda, J. Nagayama, H. Takeno, Y. Ogawa, Y. Momiyama, and M. Hashimoto, “Comparing voltage adaptation performance between replica and in-situ timing monitors,” Proc. 2018 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), San Diego, USA, Nov. 2018.
M. Hashimoto and Y. Masuda, “MTTF-aware design methodology for adaptive voltage scaling,” Proc. China Semiconductor Technology International Conference (CSTIC 2018), Shanghai, China, Mar. 2018. (invited paper)
Y. Masuda and M. Hashimoto, “MTTF-aware design methodology of error prediction based adaptively voltage-scaled circuits,” Proc. 23rd Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 159-165, Jeju, Korea, Jan. 2018.
Y. Masuda, M. Hashimoto, and T. Onoye, “Critical path isolation for time-to-failure extension and lower voltage operation,” Proc. 2016 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), Austin, Texas, USA, Nov. 2016.
Y. Masuda, M. Hashimoto, and T. Onoye, “Hardware-simulation correlation of timing error detection performance of software-based error detection mechanisms,” Proc. 2016 IEEE 22nd International Symposium on On-Line Testing and Robust System Design (IOLTS), pp. 84-89, Catalonia, Spain, July 2016.
Y. Masuda, M. Hashimoto, and T. Onoye, “Measurement of timing error detection performance of software-based error detection mechanisms and its correlation with simulation,” ACM International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU), Santa Rosa, California, USA, March 2016.
Y. Masuda, M. Hashimoto, and T. Onoye, “Performance evaluation of software-based error detection mechanisms for localizing electrical timing failures under dynamic supply noise,” Proc. 2015 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pp. 315-322, Austin Texas, USA, Nov. 2015.
S. Iizuka, Y. Masuda, M. Hashimoto, and T. Onoye, “Stochastic timing error rate estimation under process and temporal variations,” Proc. 2015 IEEE International Test Conference (ITC), Anaheim, California, USA, Sep. 2015.
Domestic Conference Papers
小森工,増田豊,石原亨, “RISC-V プロセッサにおける軽量デュアル OS 実行支援機構,” 第244回ARC・第202回SLDM・第62回EMB合同研究発表会 (ETNET2023), 天城町, 2023年3月.
T. Komori, Y. Masuda, and T. Ishihara, “DVFS Virtualization for Energy Minimization of Mixed-Criticality Dual-OS Platforms,” Work-in-Progress (WIP) sessions at Design Automation Conference (DAC), San Francisco, CA, USA, July 2022.
L. Hou, Y. Masuda, and T. Ishihara, “An Accuracy Reconfigurable Vector Accelerator based on Approximate Logarithmic Multipliers,” 電子情報通信学会 VLSI 設計技術研究会, 2022年3月 (記念講演).
T. Cheng, Y. Masuda, J. Nagayama, Y. Momiyama, J. Chen, and M. Hashimoto, “Mode-Wise Voltage-Scalable Design with Activation-Aware Slack Assignment for Energy Minimization,” 電子情報通信学会 VLSI設計技術研究会, March 2021 (記念講演、オンライン).
T. Ishihara, J. Shiomi, Y. Masuda, and R. Matsuo, “EEC: Energy Efficient Computing via Dynamic Voltage Scaling and In-Network Optical Processing,” University Booth at DATE 2020, France, Mar. 2020.
J. Nagayama, Y. Masuda, M. Takeshige, Y. Ogawa, M. Hashimoto, and Y. Momiyama, “Activation-Aware Slack Assignment (ASA) for Mode-Wise Power Saving in High-End ISP,” Design Automation Conference, Designer/IP Track, June 2019.
Y. Masuda and M. Hashimoto, “Design and test of adaptively voltage scaled circuits,” SIGDA Student Research Forum at 23rd Asia and South Pacific Design Automation Conference (SRF at ASP-DAC), Jeju, Korea, Jan. 2018.