Y. Honda, Y. Masuda, and T. Ishihara, “Feedback-tuned fuzzing for accelerating quality verification of
approximate computing design,” Proc. 29th International Symposium on On-Line Testing and Robust System Design (IOLTS), July 2023. (accepted, to appear)
J. Lu, Y. Masuda, and T. Ishihara, “An Efficient Fault Injection Algorithm for Identifying Unimportant FFs in Approximate Computing Circuits,” Proc. IEEE Design, Automation and Test in Europe Conference (DATE), Apr. 2023.
J. Lu, Y. Masuda, and T. Ishihara, “Importance Evaluation Methodology of FFs for Design Optimization of Approximate Computing Circuits,” Proc. 24th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI), pp. 20 – 25, Hirosaki, Aomori, Oct. 2022.
J. Shiomi, S. Terada, T. Ishihara, and H. Onodera, “Zero-Aware Fine-Grained Power Gating for Standard-Cell Memories in Voltage-Scaled Circuits,” Proc. IEEE 35th International System-on-Chip Conference (SOCC), pp. 1-6, Belfast, United Kingdom, Sept. 2022.
T. Komori, Y. Masuda, and T. Ishihara, “DVFS Virtualization for Energy Minimization of Mixed-Criticality Dual-OS Platforms,” Work-in-Progress (WIP) sessions at Design Automation Conference (DAC), San Francisco, CA, USA, July 2022.
A. Shinya, K. Nozaki, S. Kita, T. Ishihara, S. Matsuo, and M. Notomi, “Energy Efficient OEO Conversion and Its Applications to Photonic Integrated Systems,” Proc. IEEE Optical Fiber Communications Conference and Exhibition (OFC), pp.1-3, March 2022.
Jun Shiomi and Tohru Ishihara, “(Chapter 10) Minimum Energy Computing via Supply and Threshold Voltage Scaling (pp. 227-254),’’ in Liliana Andrade and Frederic Rousseau (Ed.), “Multi-Processor System-on-Chip 1 (March 2021),” Wiley – ISTE.
T. Y. Cheng, Y. Masuda, J. Chen, J. Yu, and M. Hashimoto, “Logarithm-Approximate Floating-Point Multiplier is Applicable to Power-Efficient Neural Network Training,’’ Integration, the VLSI Journal, vol. 74, pp. 19-31, Sep. 2020.
L. Hou, Y. Masuda, and T. Ishihara, “An Accuracy Reconfigurable Multiply-Accumulate Unit Based on Operand-Decomposed Mitchell’s Multiplier,” Proc. 23rd Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI), pp. 68-73, Mar. 2021.
N. Hattori, Y. Masuda, T. Ishihara, J. Shiomi, A. Shinya, and M. Notomi, “Optical-electronic implementation of artificial neural network for ultrafast and accurate inference processing,” Proc. AI and Optical Data Sciences II. International Society for Optics and Photonics, Mar. 2021.
T. Y. Cheng, Y. Masuda, J. Nagayama, Y. Momiyama, J. Chen, and M. Hashimoto, “Mode-wise Voltage-scalable Design with Activation-aware Slack Assignment for Energy Minimization,” Proc. Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 284 – 290, Jan. 2021.
J. Shiomi, T. Ishihara, H. Onodera, A. Shinya, and M. Notomi, “An Optical Accelerator for Deep Neural Network Based on Integrated Nanophotonics,” Proc. IEEE International Conference on Rebooting Computing (ICRC), pp. 95-101, Dec. 2020.
Y. Masuda, J. Nagayama, T. Y. Cheng, T. Ishihara, Y. Momiyama, and M. Hashimoto, “Variation-Tolerant Voltage Over-Scalable Design with Critical Path Isolation and Bit-Width Scaling,” International Workshop on Logic & Synthesis (IWLS), pp.136-142, July 2020.
R. Matsuo, J. Shiomi, T. Ishihara, H. Onodera, A. Shinya, and M. Notomi, “A Synthesis Method for Power-Efficient Integrated Optical Logic Circuits Towards Light Speed Processing,” Proc. IEEE Computer Society Annual Symposium on VLSI (ISVLSI), pp.488-493, July 2020.
T. Cheng, Y. Masuda, J. Nagayama, Y. Momiyama, J. Chen, and M. Hashimoto, “Mode-Wise Voltage-Scalable Design with Activation-Aware Slack Assignment for Energy Minimization,” 電子情報通信学会 VLSI設計技術研究会, March 2021 (招待講演).
R. Matsuo, J. Shiomi, T. Ishihara, H. Onodera, A. Shinya, and M. Notomi, “Methods for Reducing Power and Area of BDD-Based Optical Logic Circuits,” IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, vol. E102-A, no. 12, pp. 1751-1759, Dec. 2019.
H. Xu, J. Shiomi, T. Ishihara, and H. Onodera, “On-Chip Cache Architecture Exploiting Hybrid Memory Structures for Near-Threshold Computing,” IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, vol. E102-A, no. 12, pp. 1741-1750, Dec. 2019.
J. Nagayama, Y. Masuda, M. Takeshige, Y. Ogawa, M. Hashimoto, and Y. Momiyama, “Activation-Aware Slack Assignment (ASA) for Mode-Wise Power Saving in High-End ISP,” Design Automation Conference, Designer/IP Track, June 2019.