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2024 年度
学術論文誌
国際会議
国内会議
- 陳岱鋒,増田豊,石原亨, “Gain-Cell DRAMを活用する近しきい値電圧動作に適した行列積演算器,” 情報処理学会DA シンポジウム, pp. 255 – 262, 2024 年8 月.
2023 年度
学術論文誌
- J. Lu, Y. Masuda, and T. Ishihara, “Identification of redundant flip-flops using fault injection for low-power approximate computing circruits,” IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, vol.E107-A, No.3, pp.540-548, Mar. 2024.
- T. Komori, Y. Masuda, and T. Ishihara, “Virtualizing DVFS for Energy Minimization of Embedded Dual-OS Platform,” IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, vol.E107-A, No.1, pp.3-15, Jan. 2024.
国際会議
- T. -F. Chen, Y. Masuda, and T. Ishihara, “Processing-in-Memory Accelerator Design with a Fully Synthesizable Cell-based DRAM,” University Fair of DATE2024, Mar. 2024.
- T. -F. Chen, T. Komori, Y. Masuda, and T. Ishihara, “Dual-OS-based DVFS on a RISC-V Hardware Platform for Energy Efficient Real time Computing,” Workshop 07 – Enabling rapid and sustainable RISC-V based research using open source HW and SW of DATE2024, Mar. 2024.
- T. -F. Chen, Y. Masuda, and T. Ishihara, “A Design Strategy for Processing-in-Memory Accelerators Using Cell-based DRAM,” Proc. 25th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI), pp. 275 – 280, Mar. 2024.
- C. Wang, Y. Masuda, and T. Ishihara, “An optoelectronic pipelined convolutional-RNN architecture for energy-efficient AI accelerator,” Proc. 25th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI), pp. 14 – 19, Mar. 2024.
- T. -F. Chen, Y. Masuda, and T. Ishihara, “A Standard Cell Memory Based on 2T Gain Cell DRAM for Memory-Centric Accelerator Design,” Proc. 36th IEEE International System-On-Chip Conference (SOCC), pp.34-39, Sept. 2023.
- Y. Honda, Y. Masuda, and T. Ishihara, “Feedback-tuned fuzzing for accelerating quality verification of approximate computing design,” Proc. 29th International Symposium on On-Line Testing and Robust System Design (IOLTS), July 2023.
- J. Lu, Y. Masuda, and T. Ishihara, “An Efficient Fault Injection Algorithm for Identifying Unimportant FFs in Approximate Computing Circuits,” Proc. IEEE Design, Automation and Test in Europe Conference (DATE), Apr. 2023.
国内会議
- 本多 佑成,増田豊,石原亨, “計算品質を考慮した適者生存戦略に基づき近似計算の品質検証を高速化するファジングテスト手法,” 第248回ARC・第205回SLDM・第65回EMB合同研究発表会(ETNET2024), 郷ノ浦町, 2024年3月.
- 陳岱鋒,増田豊,石原亨, “Gain-Cell構造に基づく完全合成可能なスタンダードセルベースDRAM,” 情報処理学会DA シンポジウム, pp. 221 – 227, 2023 年9 月.
2022 年度
学術論文誌
- Y. Masuda, Y. Honda, and T. Ishihara, “Dynamic Verification Framework of Approximate Computing Circuits using Quality-aware Coverage-based Grey-box Fuzzing,” IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, vol.E106-A, No.3, pp.514-522, Mar. 2023.
- L. Hou, Y. Masuda, and T. Ishihara, “An Accuracy Reconfigurable Vector Accelerator based on Approximate Logarithmic Multipliers for Energy-Efficient Computing,” IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, vol.E106-A, No.3, pp.532-541, Mar. 2023.
国際会議
- J. Lu, Y. Masuda, and T. Ishihara, “Importance Evaluation Methodology of FFs for Design Optimization of Approximate Computing Circuits,” Proc. 24th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI), pp. 20 – 25, Hirosaki, Aomori, Oct. 2022.
- J. Shiomi, S. Terada, T. Ishihara, and H. Onodera, “Zero-Aware Fine-Grained Power Gating for Standard-Cell Memories in Voltage-Scaled Circuits,” Proc. IEEE 35th International System-on-Chip Conference (SOCC), pp. 1-6, Belfast, United Kingdom, Sept. 2022.
- T. Komori, Y. Masuda, and T. Ishihara, “DVFS virtualization for energy minimization of mixed-criticality dual-OS platforms,” Proc. 28th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA), pp.128-137, Taipei, Taiwan, Aug. 2022.
- N. Hattori, Y. Masuda, T. Ishihara, A. Shinya, and M. Notomi, “Power-Aware Pruning for Ultrafast, Energy-Efficient, and Accurate Optical Neural Network Design,” Proc. Design Automation Conference (DAC), pp. 1285 – 1290, doi.org/10.1145/3489517.3530405, San Francisco, CA, USA, July 2022.
- T. Komori, Y. Masuda, and T. Ishihara, “DVFS Virtualization for Energy Minimization of Mixed-Criticality Dual-OS Platforms,” Work-in-Progress (WIP) sessions at Design Automation Conference (DAC), San Francisco, CA, USA, July 2022.
- T. Ichikawa, Y. Masuda, T. Ishihara, A. Shinya, and M. Notomi, “Optoelectronic Implementation of Compact and Power-Efficient Recurrent Neural Networks,” Proc. IEEE Computer Society Annual Symposium on VLSI (ISVLSI), pp. 390-393, July 2022.
国内会議
- 小森工,増田豊,石原亨, “RISC-V プロセッサにおける軽量デュアル OS 実行支援機構,” 第244回ARC・第202回SLDM・第62回EMB合同研究発表会 (ETNET2023), 天城町, 2023年3月.
- 本多 佑成,増田豊,石原亨, “近似計算の品質検証に向けたファジングのフィードバック調整手法の一検討,” 第244回ARC・第202回SLDM・第62回EMB合同研究発表会 (ETNET2023), 天城町, 2023年3月.
- 陸 佳萱,増田豊,石原亨, “近似計算回路の低消費電力化に向けた故障挿入を用いた冗長なフリップフロッ プの特定,” 電子情報通信学会 VLSI 設計技術研究会, pp. 167 – 172, 那覇, 2023年3月.
- 香村 祐樹, 増田 豊, 石原 亨, “ファジングを用いた近似コンピューティング回路のハードウェアトロイ検出,” 第199回SLDM研究発表会, 京都, 2022年11月 (ポスター発表).
- 市川大生, 増田豊, 石原亨, 新家昭彦, 納富雅也, “省面積と低電力を両立する光電融合RNN アーキテクチャ,” 第35 回回路とシステムワークショップ論文集, pp. 412 – 417, 北九州, 2022 年8 月.
2021 年度
学術論文誌
- Y. Masuda, J. Nagayama, T. Cheng, T. Ishihara, Y. Momiyama, and M. Hashimoto, “Low-Power Design Methodology of Voltage Over-Scalable Circuit with Critical Path Isolation and Bit-Width Scaling,” IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol.E105-A, No.3, pp.509-517, Mar. 2022.
- T. Komori, Y. Masuda, J. Shiomi, and T. Ishihara, “Approximate Minimum Energy Point Tracking and Task Scheduling for Energy-Efficient Real-Time Computing,” IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol.E105-A, No.3, pp.497-508, Mar. 2022.
- T. Y. Cheng, Y. Masuda, J. Nagayama, Y. Momiyama, J. Chen, and M. Hashimoto, “Activation-aware Slack Assignment Based Mode-wise Voltage Scaling for Energy Minimization,” IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol.E105-A, No.3, pp.518-529, Mar. 2022.
- N. Hattori, J. Shiomi, Y. Masuda, T. Ishihara, A. Shinya, and M. Notomi, “Neural Network Calculations at the Speed of Light Using Optical Vector-Matrix Multiplication and Optoelectronic Activation,” IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol. E104-A, No.11, pp.1477-1487, Nov. 2021.
- R. Matsuo, J. Shiomi, T. Ishihara, H. Onodera, A. Shinya, and M. Notomi, “A Synthesis Method Based on Multi-Stage Optimization for Power-Efficient Integrated Optical Logic Circuits,” IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol. E104-A, No. 11, pp. 1546-1554, Nov. 2021.
国際会議
- A. Shinya, K. Nozaki, S. Kita, T. Ishihara, S. Matsuo, and M. Notomi, “Energy Efficient OEO Conversion and Its Applications to Photonic Integrated Systems,” Proc. IEEE Optical Fiber Communications Conference and Exhibition (OFC), pp.1-3, March 2022.
- L. Hou, Y. Masuda, and T. Ishihara, “An Accuracy Reconfigurable Vector Accelerator based on Approximate Logarithmic Multipliers,” Proc. Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 568 – 573, Jan. 2022.
- K. Yoshisue, Y. Masuda, and T. Ishihara, “Dynamic Verification of Approximate Computing Circuits using Coverage-based Grey-box Fuzzing,” Proc. 2021 IEEE 27th International Symposium on On-Line Testing and Robust System Design (IOLTS), June 2021.
- T. Komori, Y. Masuda, J. Shiomi, and T. Ishihara, “Integration of Minimum Energy Point Tracking and Soft Real-Time Scheduling for Edge Computing,” Proc. IEEE International Symposium on Quality Electronic Design (ISQED), pp. 300 – 306, Apr. 2021.
国内会議
- L. Hou, Y. Masuda, and T. Ishihara, “An Accuracy Reconfigurable Vector Accelerator based on Approximate Logarithmic Multipliers,” 電子情報通信学会 VLSI 設計技術研究会, 2022年3月 (記念講演).
- 陸 佳萱,増田豊,石原亨, “近似コンピューティング回路の設計最適化に向けた計算重要度評価技術,” 第195回SLDM研究発表会, 2021年10月 (オンライン、ポスター発表).
- 熊谷 僚太,増田豊,石原亨, “ファジングと高位合成を用いた近似コンピューティング回路のタイミング検証手法,” 第195回SLDM研究発表会, 2021年10月 (オンライン、ポスター発表).
- 本多 佑成,増田豊,石原亨, “近似コンピューティング回路の品質検証を高速化するファジングテスト法,” 第195回SLDM研究発表会, 2021年10月 (オンライン、ポスター発表).
- 小森工,増田豊,石原亨, “デュアルOSと仮想化DVFSによるミックスドクリティカルシステムの消費エネルギー最小化,” 情報処理学会DA シンポジウム, pp. 15 – 23, 2021 年9 月.
- 小森工, 増田豊, 塩見準, 石原亨, “タスクのリアルタイム応答を保証する近似最小エネルギー点追跡,” 第34 回回路とシステムワークショップ論文集, pp. 178 – 183, 2021 年8 月.
- 小森工,増田豊,塩見準,石原亨, “リアルタイムシステムにおけるプロセッサの最小エネルギー点追跡手法,” LSI とシステムのワークショップ, 2021年5月 (ポスター発表).
特許出願
- 特願2021-135353,“プロセッサシステム、プロセッサシステムの管理方法、および、コンピュータプログラム,” 小森工, 石原亨, 2021 年8 月23日.
2020 年度
学術図書
- Jun Shiomi and Tohru Ishihara, “(Chapter 10) Minimum Energy Computing via Supply and Threshold Voltage Scaling (pp. 227-254),’’ in Liliana Andrade and Frederic Rousseau (Ed.), “Multi-Processor System-on-Chip 1 (March 2021),” Wiley – ISTE.
学術論文誌
- T. Y. Cheng, Y. Masuda, J. Chen, J. Yu, and M. Hashimoto, “Logarithm-Approximate Floating-Point Multiplier is Applicable to Power-Efficient Neural Network Training,’’ Integration, the VLSI Journal, vol. 74, pp. 19-31, Sep. 2020.
国際会議
- L. Hou, Y. Masuda, and T. Ishihara, “An Accuracy Reconfigurable Multiply-Accumulate Unit Based on Operand-Decomposed Mitchell’s Multiplier,” Proc. 23rd Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI), pp. 68-73, Mar. 2021.
- N. Hattori, Y. Masuda, T. Ishihara, J. Shiomi, A. Shinya, and M. Notomi, “Optical-electronic implementation of artificial neural network for ultrafast and accurate inference processing,” Proc. AI and Optical Data Sciences II. International Society for Optics and Photonics, Mar. 2021.
- Y. Masuda, J. Nagayama, T. Y. Cheng, T. Ishihara, Y. Momiyama, and M. Hashimoto, “Critical Path Isolation and Bit-Width Scaling Are Highly Compatible for Voltage Over-Scalable Design,” Proc. IEEE Design, Automation and Test in Europe Conference (DATE), pp. 1260-1265, Feb. 2021.
- T. Y. Cheng, Y. Masuda, J. Nagayama, Y. Momiyama, J. Chen, and M. Hashimoto, “Mode-wise Voltage-scalable Design with Activation-aware Slack Assignment for Energy Minimization,” Proc. Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 284 – 290, Jan. 2021.
- J. Shiomi, T. Ishihara, H. Onodera, A. Shinya, and M. Notomi, “An Optical Accelerator for Deep Neural Network Based on Integrated Nanophotonics,” Proc. IEEE International Conference on Rebooting Computing (ICRC), pp. 95-101, Dec. 2020.
- Y. Masuda, J. Nagayama, T. Y. Cheng, T. Ishihara, Y. Momiyama, and M. Hashimoto, “Variation-Tolerant Voltage Over-Scalable Design with Critical Path Isolation and Bit-Width Scaling,” International Workshop on Logic & Synthesis (IWLS), pp.136-142, July 2020.
- K. Kiyawat, Y. Masuda, J. Shiomi, and T. Ishihara, “Real-time Minimum Energy Point Tracking Using a Predetermined Optimal Voltage Setting Strategy,” Proc. IEEE Computer Society Annual Symposium on VLSI (ISVLSI), pp.415-421, July 2020.
- R. Matsuo, J. Shiomi, T. Ishihara, H. Onodera, A. Shinya, and M. Notomi, “A Synthesis Method for Power-Efficient Integrated Optical Logic Circuits Towards Light Speed Processing,” Proc. IEEE Computer Society Annual Symposium on VLSI (ISVLSI), pp.488-493, July 2020.
国内会議
- 増田豊, “集積回路の潜在能力を100%引き出す設計技術,” 情報処理学会第83 回全国大会 IPSJ-ONE 2021, 2021 年3 月 (招待講演).
- T. Cheng, Y. Masuda, J. Nagayama, Y. Momiyama, J. Chen, and M. Hashimoto, “Mode-Wise Voltage-Scalable Design with Activation-Aware Slack Assignment for Energy Minimization,” 電子情報通信学会 VLSI設計技術研究会, March 2021 (招待講演).
- 吉末和樹,増田豊,石原亨,“ファジングを用いた近似コンピューティング回路の品質検証手法の一検討,” デザインガイア,2020年11月.
- 増田豊, 長山準, 鄭泰禹, 石原亨, 籾山陽一, 橋本昌宜, “クリティカルパス・アイソレーションとビット幅削減を用いた過電圧スケーリング向け省電力設計手法,” 情報処理学会DA シンポジウム, pp. 44-51, 2020年9 月.
- 服部直樹, 増田豊, 石原亨, 塩見準, 新家昭彦, 納富雅也, “集積ナノフォトニクスに基づく光ニューラルネットワークを対象とした回路アーキテクチャ探索,” 第33回 回路とシステムワークショップ論文集, pp. 10-15, 2020年8月.
2019 年度
学術論文誌
- R. Matsuo, J. Shiomi, T. Ishihara, H. Onodera, A. Shinya, and M. Notomi, “Methods for Reducing Power and Area of BDD-Based Optical Logic Circuits,” IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, vol. E102-A, no. 12, pp. 1751-1759, Dec. 2019.
- H. Xu, J. Shiomi, T. Ishihara, and H. Onodera, “On-Chip Cache Architecture Exploiting Hybrid Memory Structures for Near-Threshold Computing,” IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, vol. E102-A, no. 12, pp. 1741-1750, Dec. 2019.
- Y. Masuda and M. Hashimoto, “MTTF-Aware Design Methodology of Adaptively Voltage Scaled Circuit with Timing Error Predictive Flip-Flop,” IEICE Trans. on Fundamentals of Electronics, Communications, and Computer Sciences, vol. 102-A, no. 7, July 2019.
- T. Koyanagi, J. Shiomi, T. Ishihara, and H. Onodera, “A Design Method of a Cell-Based Amplifier for Body Bias Generation,” IEICE Trans. on Electronics, vol. E102-C, no. 7, pp. 565-572, Jul. 2019.
国際会議
- T. Ishihara, J. Shiomi, N. Hattori, Y. Masuda, A. Shinya, and M. Notomi, “An Optical Neural Network Architecture based on Highly Parallelized WDM-Multiplier-Accumulator,” Workshop of Photonics-Optics Technology Oriented Networking, Information, and Computing Systems (PHOTONICS), Nov. 2019.
- J. Nagayama, Y. Masuda, M. Takeshige, Y. Ogawa, M. Hashimoto, and Y. Momiyama, “Activation-Aware Slack Assignment (ASA) for Mode-Wise Power Saving in High-End ISP,” Design Automation Conference, Designer/IP Track, June 2019.
国内会議
- 富山葉月, 増田豊, 石原亨, “遅延故障に起因する回路寿命分布の確率的高速推定手法,” 信学技報, vol. 119, no. 443, VLD2019-113, HWS2019-86, pp. 113-118, 2020年3月.
- 服部直樹, 増田豊, 石原亨, 塩見準, 新家昭彦, 納富雅也, “ニューラルネットワークの集積ナノフォトニクス実装に適した回路構造探索,” 信学技報, vol. 119, no. 443, VLD2019-137, HWS2019-110, pp. 251-256, 2020年3月.
- 富山葉月,増田豊,石原亨,“待ち行列理論を用いた確率的回路寿命推定シミュレータの高速化,” 電気関係学会関西連合大会, 大阪, 2019年11月.
- 服部直樹, 増田豊, 石原亨, “集積ナノフォトニクスに基づく光ニューラルネットワーク,” ET&IoT Technology 2019, 横浜, 2019年11月. (ポスター発表)
- 富山葉月, 増田豊, 石原亨, “確率的回路寿命推定シミュレータの高速化,” ET&IoT Technology 2019, 横浜, 2019年11月. (ポスター発表)
- 塩見凖、石原亨, 小野寺秀俊, 新家昭彦, 納富雅也 “集積ナノフォトニクスに基づく近似並列乗算器を用いた低レイテンシ光ニューラルネットワーク,” デザインガイア2019, pp. 1-6, 2019年11 月.
- 今井悠貴, 塩見凖, 石原亨, 小野寺秀俊, 新家昭彦, 納富雅也, “波長分割多重を用いたブース法に基づく光並列乗算器の構成手法,” 情報処理学会 DAシンポジウム2019, 2019年8月.
- 松尾亮祐, 塩見凖, 小野寺秀俊, 石原亨, 新家昭彦, 納富雅也, “二分決定グラフに基づく光論理回路の消費電力削減手法,” 情報処理学会 DAシンポジウム2019, 2019年8月.
- 内田翼, 塩見準, 石原亨, 小野寺秀俊, “広範囲な電圧領域で動作するフリップフロップのタイミング特性モデル,” 情報処理学会 DAシンポジウム2019, 2019年8月.
- S. Liu, J. Shiomi, T. Ishihara, H. Onodera, “A Process-Scheduler-Based Approach to Minimum Energy Point Tracking,” IPSJ DA Symposium, pp. 166-171, Kaga, Aug. 2019 (poster).