R. Matsuo, J. Shiomi, T. Ishihara, H. Onodera, A. Shinya, and M. Notomi, “A Synthesis Method Based on Multi-Stage Optimization for Power-Efficient Integrated Optical Logic Circuits,” IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, (accepted, to appear).
国際会議
T. Komori, Y. Masuda, J. Shiomi, and T. Ishihara, “Integration of Minimum Energy Point Tracking and Soft Real-Time Scheduling for Edge Computing,” Proc. IEEE International Symposium on Quality Electronic Design (ISQED), pp. 300 – 306, Apr. 2021.
2020 年度
学術図書
Jun Shiomi and Tohru Ishihara, “(Chapter 10) Minimum Energy Computing via Supply and Threshold Voltage Scaling (pp. 227-254),’’ in Liliana Andrade and Frederic Rousseau (Ed.), “Multi-Processor System-on-Chip 1 (March 2021),” Wiley – ISTE.
学術論文誌
T. Y. Cheng, Y. Masuda, J. Chen, J. Yu, and M. Hashimoto, “Logarithm-Approximate Floating-Point Multiplier is Applicable to Power-Efficient Neural Network Training,’’ Integration, the VLSI Journal, vol. 74, pp. 19-31, Sep. 2020.
国際会議
L. Hou, Y. Masuda, and T. Ishihara, “An Accuracy Reconfigurable Multiply-Accumulate Unit Based on Operand-Decomposed Mitchell’s Multiplier,” Proc. 23rd Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI), pp. 68-73, Mar. 2021.
N. Hattori, Y. Masuda, T. Ishihara, J. Shiomi, A. Shinya, and M. Notomi, “Optical-electronic implementation of artificial neural network for ultrafast and accurate inference processing,” Proc. AI and Optical Data Sciences II. International Society for Optics and Photonics, Mar. 2021.
Y. Masuda, J. Nagayama, T. Y. Cheng, T. Ishihara, Y. Momiyama, and M. Hashimoto, “Critical Path Isolation and Bit-Width Scaling Are Highly Compatible for Voltage Over-Scalable Design,” Proc. IEEE Design, Automation and Test in Europe Conference (DATE), pp. 1260-1265, Feb. 2021.
T. Y. Cheng, Y. Masuda, J. Nagayama, Y. Momiyama, J. Chen, and M. Hashimoto, “Mode-wise Voltage-scalable Design with Activation-aware Slack Assignment for Energy Minimization,” Proc. Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 284 – 290, Jan. 2021.
J. Shiomi, T. Ishihara, H. Onodera, A. Shinya, and M. Notomi, “An Optical Accelerator for Deep Neural Network Based on Integrated Nanophotonics,” Proc. IEEE International Conference on Rebooting Computing (ICRC), pp. 95-101, Dec. 2020.
Y. Masuda, J. Nagayama, T. Y. Cheng, T. Ishihara, Y. Momiyama, and M. Hashimoto, “Variation-Tolerant Voltage Over-Scalable Design with Critical Path Isolation and Bit-Width Scaling,” International Workshop on Logic & Synthesis (IWLS), pp.136-142, July 2020.
K. Kiyawat, Y. Masuda, J. Shiomi, and T. Ishihara, “Real-time Minimum Energy Point Tracking Using a Predetermined Optimal Voltage Setting Strategy,” Proc. IEEE Computer Society Annual Symposium on VLSI (ISVLSI), pp.415-421, July 2020.
R. Matsuo, J. Shiomi, T. Ishihara, H. Onodera, A. Shinya, and M. Notomi, “A Synthesis Method for Power-Efficient Integrated Optical Logic Circuits Towards Light Speed Processing,” Proc. IEEE Computer Society Annual Symposium on VLSI (ISVLSI), pp.488-493, July 2020.
T. Cheng, Y. Masuda, J. Nagayama, Y. Momiyama, J. Chen, and M. Hashimoto, “Mode-Wise Voltage-Scalable Design with Activation-Aware Slack Assignment for Energy Minimization,” 電子情報通信学会 VLSI設計技術研究会, March 2021 (招待講演).
R. Matsuo, J. Shiomi, T. Ishihara, H. Onodera, A. Shinya, and M. Notomi, “Methods for Reducing Power and Area of BDD-Based Optical Logic Circuits,” IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, vol. E102-A, no. 12, pp. 1751-1759, Dec. 2019.
H. Xu, J. Shiomi, T. Ishihara, and H. Onodera, “On-Chip Cache Architecture Exploiting Hybrid Memory Structures for Near-Threshold Computing,” IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, vol. E102-A, no. 12, pp. 1741-1750, Dec. 2019.
Y. Masuda and M. Hashimoto, “MTTF-Aware Design Methodology of Adaptively Voltage Scaled Circuit with Timing Error Predictive Flip-Flop,” IEICE Trans. on Fundamentals of Electronics, Communications, and Computer Sciences, vol. 102-A, no. 7, July 2019.
T. Koyanagi, J. Shiomi, T. Ishihara, and H. Onodera, “A Design Method of a Cell-Based Amplifier for Body Bias Generation,” IEICE Trans. on Electronics, vol. E102-C, no. 7, pp. 565-572, Jul. 2019.
国際会議
T. Ishihara, J. Shiomi, N. Hattori, Y. Masuda, A. Shinya, and M. Notomi, “An Optical Neural Network Architecture based on Highly Parallelized WDM-Multiplier-Accumulator,” Workshop of Photonics-Optics Technology Oriented Networking, Information, and Computing Systems (PHOTONICS), Nov. 2019.
J. Nagayama, Y. Masuda, M. Takeshige, Y. Ogawa, M. Hashimoto, and Y. Momiyama, “Activation-Aware Slack Assignment (ASA) for Mode-Wise Power Saving in High-End ISP,” Design Automation Conference, Designer/IP Track, June 2019.
S. Liu, J. Shiomi, T. Ishihara, H. Onodera, “A Process-Scheduler-Based Approach to Minimum Energy Point Tracking,” IPSJ DA Symposium, pp. 166-171, Kaga, Aug. 2019 (poster).